Correct Answer - Option 1 : Relatively very large addressing modes
Combinational logic units, which have a finite number of gates and can create specified outputs dependent on the instructions used to activate those responses, are used to implement hardwired control units. Their design is based on a fixed architecture, which requires wiring adjustments if the instruction set is updated or modified. In computers with a small instruction set, this design is preferable (RISC).
The main idea is to simplify hardware by using an instruction set consisting of a few basic steps for loading, evaluating, and storing operations, similar to how a load command loads data and a store command stores it.
RISC processors provide very few addressing modes: often just one or two. A large Number of Registers: Since RISC processors use register-to-register operations, we need to have a large number of registers.
Characteristic of RISC –
- Simpler instruction, hence simple instruction decoding.
- Instruction comes undersize of one word.
- Instruction takes a single clock cycle to get executed.
- More general-purpose registers.
- Simple Addressing Modes.
- Fewer Data types.
- The pipeline can be achieved.
RISC |
CISC |
Reduced Instruction Set Architecture |
Complex Instruction Set Architecture |
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Focus on hardware |
Uses only Hardwired control unit |
Uses both hardwired and microprogrammed control unit |
Transistors are used for more registers |
Transistors are used for storing complex
Instructions |
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Variable sized instructions |
Can perform only Register to Register Arithmetic operations |
Can perform REG to REG or REG to MEM or MEM to MEM |
Requires more number of registers
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Requires less number of registers
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Code size is small |
An instruction executed in a single clock cycle |
Instruction takes more than one clock cycle
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