# Consider a 33 MHz CPU-based system. What is the number of wait states required if it is interfaced with a 60ns memory ? Assume a maximum of 10 ns dela

77 views
in Computer
closed
Consider a 33 MHz CPU-based system. What is the number of wait states required if it is interfaced with a 60ns memory ? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.

by (30.0k points)
selected

Correct Answer - Option 4 : 3

The correct answer is "option 4".

CONCEPT:

When a computer processor accesses any external memory or the device that is slow to respond then the delay experienced by the processor is called Wait State.

Since processor speed is faster than memory chips, the processor may sit idle for some cycles due to slow memory access.

So, the total number of wait states can be defined as the total number of cycles needed by the CPU.

CALCULATION:

Memory access time = 60 ns

Total memory access time = Memory access time + Additional delay

= 60 ns + 10 ns = 70 ns

CPU Frequency = 33MHz

Clock time = $\frac{1}{33MHz}$ → $\frac{1}{33*10^6}$ns → $\frac{1}{33}$ × 10-6 ns

30.30 ns

No. of wait states = $\left\lceil\frac{70\ ns}{30.30\ ns} \right\rceil$= 3

Hence , the number of wait states required is 3.

1. Clock rate or clock frequency is one of the important factors to measure processor performance.