Question

What is the maximum input frequency limit a 3-bit Ripple counter configured around flip-flop, with inherent propagation delay time t_pd = 50 ns?
1. 6670 MHz
2. 667 MHz
3. 66.7 MHz
4. 6.67 MHz

Answer 1

Correct Answer - Option 4 : 6.67 MHz

Concept:

In Ripple counters, the carry ripples through, or propagates through every flip-flop, i.e. the propagation delays of all the flip-flops are added to get the overall delay in the counter.

For the counter to work properly, the next clock pulse must arrive when all the carry's generated are propagated through all the flip-flops and the output is stable. This can be mathematically stated as:

For the ripple counter to count properly:

T_CLK ≥ n (t_pd)FF

T_CLK = Clock Interval, and is the inverse of f_CLK, i.e.

\(f_{CLK}≤ \frac{1}{n\times (t_{pd})_{FF}}\)

Calculation:

n = 3 bits, and (t_pd)_FF = 10 ns

The maximum clock frequency will be:

\(f_{CLK}≤ \frac{1}{3\times 50n}\)

f_CLK ≤ 6.67 MHz