Question

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is_________.

Answer 1

Data:

Clock rate for non-pipeline = 2.5 GHz

CPI for non-pipeline = 4

Clock rate for pipeline = 2 GHz

CPI for pipeline = 1

Formula:

Speed up = \(\frac{{Execution\;time\left( {non\;pipeline} \right)}}{{Execution\;time\;\left( {pipeline} \right)}}\)

Execution time = CPI × Cycle time (CPI is cycles per instruction)

\({\rm{Cycle\;time\;}} = \frac{1}{{{\rm{clock\;rate}}}}\)

Calculation:

Execution time for non-pipeline = \(4 \times \frac{1}{{2.5}} = 1.6\;ns\)

Execution time for pipeline = \(1 \times \frac{1}{2} = 0.5\;ns\)

Speed up = \({{1.6}}{{0.5}} = 3.2\)