Question

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
1. 0110110…
2. 0100100…
3. 011101110…
4. 011001100…

Answer 1

Correct Answer - Option 1 : 0110110…

Qprev	D	J	K	J K next
-	1	0	0	1
0	0	1	1	1
1	1	1	1	0
1	1	0	0	0
0	0	1	1	1
1	1	1	1	0

 

Output for next cycle is in the sequence 0110110……

Here, it is given that JK flip flop toggles when J = K = 1 and it will remain same if J = K = 0. Also output of D flip flop will remain same as input.

Initially, D = 1, J = K = 0

After clock 1: D = 0 (because D gets input as 0 from initial output of J = K)

J = K = 1 (from initial output of D, so output will toggle from 0 to 1)

After clock 2: D = 1, J = K = 1 (it will retain its value, from previous output of D)

After clock 3: D = 1, J = K = 0

After clock 4: D = 0, J = K = 1

After clock 5: D = 1, J = K = 1

So, bit sequence that is generated from this is 0110110……