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Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:

i) a naïve pipeline implementation (NP) with 5 stages and

ii) an efficient pipeline (ER) where the OF stage is divided into stages OF1 and OF2 with execution times of 12ns and 8ns respectively.

The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards in _______.

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Formula:

Execution time in case of pipeline implantation = ( k + n - 1) × Tp

Where, k= number of stages

n = number of instructions

Tp= maximum stage delay + buffer delay

Speed up = \(\frac{{Execution\;time\;of\;naive\;pipeline}}{{Execution\;time\;of\;efficient\;pipeline}}\)

Calculation:

Here, total number of instructions are = 20

CASE 1: For naïve pipeline

K = 5

Stage delays are given as: 5, 4,20, 10, 3

Buffer delay = 2 ns

Clock time (Tp) = max {5,4, 20, 10, 3 } + buffer delay = 20 + 2 = 22ns

Execution time (Enp) = (5 + 20 - 1 ) × 22  = 528 ns

CASE 2: For efficient pipeline

K = 6

As OF stage is divides into two stages with delay of 12ns and 8 ns.

Clock time (Tp) = max { 5, 4, 12, 8, 10, 3} + buffer delay = 12 + 2 =14 ns

Execution time (Eep) = (6 + 20 - 1 ) × 14 = 350 ns

So, speed up = \(\frac{{528}}{{350}}\) = 1.508

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