Question

Consider a non-pipelined processor with a clock rate of 2.5 GHz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 GHz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is

1. 3.2
2. 3.0
3. 2.2
4. 2.0

Answer 1

Correct Answer - Option 1 : 3.2

Let n be the number of instructions

Non-pipelined processor:

1 instruction = 4 Clock

Frequency = 2.5 GHz

Time taken per clock = \(\frac{1}{{2.5 GHz}} = 0.4 ns\)

Time taken without pipeline per instruction = 4 × 0.4 ns

Total time taken without pipeline (Twp) = n × 4 × 0.4 ns

Pipelined processor:

Under ideal condition every instruction takes 1 Clock

1 instruction = 1 Clock

Frequency = 2 GHz

Time taken per clock = \(\frac{1}{{2GHz}} = 0.5ns\)

Time with pipeline per instruction = 1 × 0.5 ns

Total time taken with pipeline (Tp) = n × 1 × 0.5 ns

\({S_{up}} = \frac{{{{\rm{T}}_{{\rm{wp}}}}}}{{{T_p}}}\)

\({S_{up}} = \frac{{{\rm{n}} \times 4 \times 0.4}}{{n \times 1 \times 0.5}}\)

\({S_{up}} = 3.2\)

 The speed up achieved in this pipelined processor is 3.2