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When memory write or I/O read are active, data remains ______ of the processor.
1. Input
2. Output
3. Processor
4. None of these

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Correct Answer - Option 2 : Output

Control and Status Signals:

This group contains:

  • Two control signals (\(\overline {RD} \;and\;\overline {WR} )\) 
  • Three status signals (IO/M̅, S1 and S0) to identify the nature of the operation
  • One special signal (ALE) to indicate the beginning of the operation.


ALE: (Address Latch Enable)

It indicates that the bits on AD7 - AD0 are address bits.

This signal is used to latch the lower order address from multiplexed bus and generate a separate set of eight address lines A7 – A0.

\(\overline {{\bf{RD}}} - {\bf{Read}}:\)

This is a Read control signal (active low).

This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus.

\(\overline {{\bf{WR}}} - {\bf{Write}}:\)

This is a Write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location.

\({\bf{IO}}/{\bf{\bar M}}:\)

This is a status signal used to differentiate between I/O and memory operations.

When it is high, it indicates an I/O operation; when it is low, it indicates a memory operation.

This signal is combined with \(\overline {{\rm{RD}}} \left( {{\rm{Read}}} \right)\;{\rm{and\;}}\overline {{\rm{WR}}} {\rm{\;}}\left( {{\rm{Write}}} \right)\) to generate I/O and memory control signals.

S1 and S0:

These status signals, similar to \({\rm{IO}}/{\rm{\bar M}}\), can identify various operations, but they are rarely used in small systems.

(All the operations and their associated status signals are listed in Table)

Machine Cycle

Status

Control signals

IO/M̅

S1

S0

Opcode Fetch

0

1

1

\(\overline {{\rm{RD}}} = 0\)

Memory Read

0

1

0

\(\overline {{\rm{RD}}} = 0\)

Memory Write

0

0

1

\(\overline {{\rm{WR}}} = 0\)

I/O Read

1

1

0

\(\overline {{\rm{RD}}} = 0\)

I/O Write

1

0

1

\(\overline {{\rm{WR}}} = 0\)

Interrupt Acknowledge

1

1

1

\(\overline {{\rm{INTA}}} = 0\)

 

From the above table, when memory write or I/O read are active, data remains output of the processor.

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