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in Electronics by (52.3k points)

Explain the formation of depletion regions due to gate potential and also drain-source voltage.

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Consider an n-channel FET. The pn junctions are formed by the n-channel and p-type gate. These pn junctions are always reverse biased.

The two pn junctions are reverse biased by source VGG.

As the pn junctions are reverse biased, there will be only immobile positive and negative ions near the pn junction which is called depletion region. The extension of depletion region of n.

Channel FET is heavily doped, the depletion region extends more towards n region. The reverse bias on there pn junctions can also be achieved by applying a voltage across source and drain. The source VDD is applied across drain to source. The drain to source voltage produces reverse bias across the gate-source junction. VDD makes the electrons flow from the source to drain through the channel and circuited. This reverse bias creates depletion regions within the channel.

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