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Which of the following is NOT one of the analog to digital (A/D) conversion techniques?
1. Single slope integration method
2. Successive approximation method
3. Voltage to-time conversion method
4. Voltage to frequency conversion method

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Correct Answer - Option 1 : Single slope integration method

Different Analog to digital conversion techniques:

1. Direct-conversion or Flash type:

  • A direct-conversion or flash ADC has a bank of comparators sampling the input signal in parallel, each firing for a specific voltage range.
  • The comparator bank feeds a logic circuit that generates a code for each voltage range.
  • ADCs of this type have a large die size and high power dissipation.
  • They are often used for video, wideband communications, or other fast signals in optical and magnetic storage.


2. Successive approximation:

  • A successive-approximation ADC uses a comparator and a binary search to successively narrow a range that contains the input voltage.
  • At each successive step, the converter compares the input voltage to the output of an internal digital to analog converter which initially represents the midpoint of the allowed input voltage range.
  • At each step in this process, the approximation is stored in a successive approximation register (SAR) and the output of the digital to analog converter is updated for comparison over a narrower range.


3. Ramp-compare:

  • A ramp-compare ADC produces a saw-tooth signal that ramps up or down then quickly returns to zero.
  • When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fire, and the timer's value is recorded.
  • Timed ramp converters can be implemented economically, However, the ramp time may be sensitive to temperature because the circuit generating the ramp is often a simple analog integrator. A more accurate converter uses a clocked counter driving a DAC. 


4. Wilkinson:

  • The Wilkinson ADC is based on the comparison of an input voltage with that produced by a charging capacitor.
  • The capacitor is allowed to charge until a comparator determines it matches the input voltage. Then, the capacitor is discharged linearly.
  • The time required to discharge the capacitor is proportional to the amplitude of the input voltage.
  • While the capacitor is discharging, pulses from a high-frequency oscillator clock are counted by a register. The number of clock pulses recorded in the register is also proportional to the input voltage.


5. Integrating:

  • An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown input voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period).
  • Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-down period).
  • The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period. 

 

6. Charge balancing ADC:

  • The principle of charge balancing ADC is to first convert the input signal to a frequency using a voltage-to-frequency converter.
  • This frequency is then measured by a counter and converted to an output code proportional to the analog input.
  • The main advantage of these converters is that it is possible to transmit frequency even in a noisy environment or in an isolated form.
  • However, the limitation of this circuit is that the output of the voltage-to-frequency converter depends upon an RC product whose value cannot be accurately maintained over temperature and time.


7. Dual-slope ADC

  • The analog part of the circuit consists of a high input impedance buffer, precision integrator and a voltage comparator.
  • The converter first integrates the analog input signal for a fixed duration and then it integrates an internal reference voltage of opposite polarity until the integrator output is zero.
  • The main disadvantage of this circuit is the long duration time.
  • They are particularly suitable for accurate measurement of slowly varying signals such as thermocouples and weighing scales.


8. Delta-encoded:

  • A delta-encoded or counter-ramp ADC has an up-down counter that feeds a digital to analog converter (DAC).
  • The input signal and the DAC both go to a comparator.
  • The comparator controls the counter.
  • The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output matches the input signal and the number is read from the counter. 


9. Pipelined

  • A pipelined ADC (also called a sub-ranging quantizer) uses two or more conversion steps.
  • First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC).
  • This difference is then converted more precisely, and the results are combined in the last step.
  • This can be considered a refinement of the successive-approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. 


10. Sigma-delta

  • A sigma-delta ADC (also known as a delta-sigma ADC) oversamples the incoming signal by a large factor using a smaller number of bits than required are converted using a flash ADC and filters the desired signal band.
  • The resulting signal, along with the error generated by the discrete levels of the flash, is fed back and subtracted from the input to the filter.
  • This negative feedback has the effect of noise shaping the quantization error that it does not appear in the desired signal frequencies.
     

11. Time-interleaved

  • A time-interleaved ADC uses M parallel ADCs where each ADC samples data every Mth cycle of the effective sample clock.
  • The result is that the sample rate is increased M times compared to what each individual ADC can manage.
  • In practice, the individual differences between the M ADCs degrade the overall performance reducing the spurious-free dynamic range (SFDR). 
     

12. Intermediate FM stage

  • An ADC with an intermediate FM stage first uses a voltage-to-frequency converter to produce an oscillating signal with a frequency proportional to the voltage of the input signal and then uses a frequency counter to convert that frequency into a digital count proportional to the desired signal voltage.
  • Longer integration times allow for higher resolutions.
  • Likewise, the speed of the converter can be improved by sacrificing resolution.


13. A/D Using Voltage To Time Conversion:

  • In this, the cycles of variable frequency sources are counted for a fixed period.
  • It is possible to make an A/D converter by counting the cycles of a fixed-frequency source for a variable period.
  • For this, the analog voltage is required to be converted to a proportional time period.


14. Single-Slope ADC:

  • The simplest form of an integrating ADC uses a single-slope architecture.
  • In this, an unknown input voltage is integrated and the value is compared against a known reference value.
  • The time it takes for the integrator to trip the comparator is proportional to the unknown voltage. In this case, the known reference voltage must be stable and accurate to guarantee the accuracy of the measurement.

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