Question

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁ , I₂ , I₃ ,......I₁₂ is executed in this pipelined processor. Instruction 4 I is the only branch instruction and its branch target is I₉ . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is 

(A) 132 

(B) 165 

(C) 176 

(D) 328

Answer 1

Correct option is (C) 176 

Total clock slots taken are 16. Each slot will take maximum of {5, 7, 10, 8 ,7} = 10.

Hence total slots for all the instructions = 16 x 10 + 16 (pipeline delay) = 176